`timescale 1ns/1ps
module N_bit_adder_tb;
    reg [7:0] i1, i2;
    wire [7:0] answer;
    wire carry_out;
    
    // File descriptor for the log file
    integer log_file;

    // Instantiate the Unit Under Test (UUT)
    N_bit_adder uut (
        .input1(i1), 
        .input2(i2), 
        .answer(answer),
        .carry_out(carry_out)
    );

    // Initialization and test cases
    initial begin
        // Open the log file
        log_file = $fopen("simulation_results.log", "w");
        
        // Check if file was opened successfully
        if (log_file == 0) begin
            $display("Error opening log file.");
            $finish;
        end

        #100
        // Apply test vectors and write to log
        i1 = 8'd230; i2 = 8'd10;
        #100;
        $fdisplay(log_file, "i1 = %d, i2 = %d, answer = %d, carry_out = %b", i1, i2, answer, carry_out);

        i1 = 8'd256; i2 = 8'd1;
        #100;
        $fdisplay(log_file, "i1 = %d, i2 = %d, answer = %d, carry_out = %b", i1, i2, answer, carry_out);

        i1 = 8'd255; i2 = 8'd253; // Negative values in unsigned representation
        #100;
        $fdisplay(log_file, "i1 = %d, i2 = %d, answer = %d, carry_out = %b", i1, i2, answer, carry_out);

        i1 = 8'd100; i2 = 8'd200;
        #100;
        $fdisplay(log_file, "i1 = %d, i2 = %d, answer = %d, carry_out = %b", i1, i2, answer, carry_out);

        i1 = 8'd30; i2 = 8'd70;
        #100;
        $fdisplay(log_file, "i1 = %d, i2 = %d, answer = %d, carry_out = %b", i1, i2, answer, carry_out);

        i1 = 8'd2; i2 = 8'd1;
        #100;
        $fdisplay(log_file, "i1 = %d, i2 = %d, answer = %d, carry_out = %b", i1, i2, answer, carry_out);

        // Close the log file
        $fclose(log_file);
        
        $finish; // End simulation
    end
endmodule